1. Field of the Invention
The present invention relates to a silicon product wafer obtained by heat treating a silicon “substrate” wafer which has been sliced from a silicon single crystal ingot, and has not been subjected to any prior heat treatment, and in particular to a high quality silicon wafer with minimal and preferably no crystal defects in semiconductor device forming regions by suppressing occurrences of slip dislocations and warpage, and to a manufacturing method therefor.
2. Background Art
Silicon wafers used as substrates for semiconductor devices and the like are manufactured by slicing a silicon single crystal ingot, and processing the sliced wafers, for example by processing steps including heat treatment, mirror polishing, and the like. The Czochralksi method (CZ) is one manufacturing method for producing such silicon single crystal ingots, and also is the most common method, since it is relatively easy to obtain single crystal ingots with a large diameters while also exerting control over defects.
Silicon single crystals (CZ-Si) pulled by the CZ method always contain crystal defects called “grown-in defects”. Oxygen dissolves in the CZ-Si lattice (interstitial oxygen) in a supersaturated state, and the supersaturated oxygen, through oxygen precipitation, produces fine defects called “BMDs” (Bulk Micro Defects) in subsequent heat treatments (anneals) conducted.
In order to construct a semiconductor device on a silicon wafer, it is required that no crystal defects are present in the semiconductor device forming region. When crystal defects are present in the surface on which a circuit is desired to be formed, however, an open circuit or the like is frequently caused by the defect. Meanwhile, however, it is also required that the silicon wafer include BMDs in a proper amount therein. The BMDs serve to getter metal impurities and the like. Metal impurities are one cause of semiconductor device malfunction.
In order to address the above requirements, silicon wafers are subjected to a high-temperature anneal to induce BMDs in the silicon wafer to form an IG (intrinsic gettering) layer, and also to diminish grown-in defects present in the surface of the silicon wafer to form a DZ denuded zone (“DZ”) layer where crystal defects are preferably completely absent. As a specific example of such a process, a nitrogen-doped substrate, or a substrate doped with both nitrogen and hydrogen is high-temperature annealed to reduce grown-in defects on the surface of the substrate, and form BMDs in the substrate core. (JP-A-10-98047 and JP-A-2000-281491).
However, oxygen concentrations in the DZ layers formed on the front surface and a back surface of the silicon wafer in the high-temperature annealing process are extremely reduced due to out-diffusion of oxygen during heat treatment. As a result, restraint of propagation of dislocation defects from the wafer front and back surfaces is considerably reduced, and slips (dislocation defects) easily extend from the fine flaws on the surfaces introduced during the annealing process into the bulk of the wafer. As a result, the strength of the silicon wafer is reduced due to propagation of such slip dislocations. For example, when a silicon wafer is annealed while supported by heat treatment pins or the like, slip dislocations often extend from the supported portions across the back face of the wafer, and through to the front surface. Slip dislocations may also extend from the silicon wafer edge portion.
When the strength of the silicon wafer is lowered, there is a concern that wafers may become damaged or broken during wafer processing or device fabrication steps. However, a DZ layer is often necessary for semiconductor device formation, and thus a silicon wafer that has a DZ layer but also exhibits excellent strength properties has been required.
In conventional wafer processing, as disclosed in JP-A-10-98047 or JP-A-2000-281491, attention was not directed to maintaining the strength of the silicon wafers, and silicon wafers manufactured by the disclosed processes cannot avoid slip dislocation propagation.
In order to prevent the occurrence of slip dislocations, a method for generating BMDs at a high density has been proposed. Specifically, silicon wafers with oxygen precipitation nuclei with sizes of ≦20 nm in an amount of 1×1010 atoms/cm3 or more are formed in the BMD layer by heat treating a substrate sliced from a silicon signal crystal ingot at a temperature of 500 to 1200° C. for a time of 1 to 600 minutes under a mixed gas atmosphere consisting of nitrogen gas and inert gas, or a mixed gas of ammonia and inert gas wherein the heating and cooling rates are rapid. (JP-A-2006-40980). In JP-A-08-213403, BMDs in a high concentration of 1×1010 atoms/cm3 to 1×1012 atoms/cm3 are generated in silicon wafers by repeating heat treatment steps several times.
For large diameter silicon wafers, rapid heating and cooling rates prior to and after heat treatment, for example when using a Rapid Thermal Annealer (RTA), warpage becomes problematic in addition to slip dislocations.
An illustrative diagram of slips and warpage introduced by the RTA heat treatment is shown in FIG. 1. Slips are introduced from a contacting point between a wafer back surface and a wafer support pin. The slips introduced propagate in a 110 direction, which causes wafer damage or even breakage in some cases. Warpage is a phenomenon where a wafer is deformed due to heat strain during the RTA heat treatment. In a wafer of 100 orientation, for example, a mountain-shaped portion and a valley-shaped portion appear, as shown in FIG. 1. Warpage of silicon wafers as shipped is generally equal to or less than 10 μm. However, following RTA, a difference in height between the mountain and the valley portions may reach several tens of μm. When warpage becomes large, a semiconductor device pattern cannot be properly focused on the wafer surface, resulting in a decrease in semiconductor device yield. High densities of slip dislocation are present in silicon wafers where large warpage has occurred. It is believed that these slip dislocations cause the warpage.
Warp becomes especially significant when the wafer diameter becomes greater than or equal to 200 mm, and in such wafers it is impossible to avoid the problem only by establishing a high BMD concentration, as discussed above.
Thus, there has been a great demand for silicon wafers of high quality which do not include crystal defects in the semiconductor device forming region, wherein slip dislocations and warp are suppressed during device manufacturing, and also a manufacturing technique therefor.